EDSEL=OFF, SOURCESEL=NONE
Channel Control Register
| SIGSEL | Signal Select |
| SOURCESEL | Source Select 0 (NONE): No source selected 1 (PRSL): Peripheral Reflex System 2 (ACMP0): Analog Comparator 0 3 (ACMP1): Analog Comparator 1 4 (ADC0): Analog to Digital Converter 0 5 (RTCC): Real-Time Counter and Calendar 6 (GPIOL): General purpose Input/Output 7 (GPIOH): General purpose Input/Output 8 (LETIMER0): Low Energy Timer 0 9 (PCNT0): Pulse Counter 0 10 (CRYOTIMER): CRYOTIMER 11 (CMU): Clock Management Unit 17 (VDAC0): Digital to Analog Converter 0 18 (LESENSEL): Low Energy Sensor Interface 19 (LESENSEH): Low Energy Sensor Interface 20 (LESENSED): Low Energy Sensor Interface 21 (LESENSE): Low Energy Sensor Interface 32 (USART0): Universal Synchronous/Asynchronous Receiver/Transmitter 0 33 (USART1): Universal Synchronous/Asynchronous Receiver/Transmitter 1 34 (USART2): Universal Synchronous/Asynchronous Receiver/Transmitter 2 35 (USART3): Universal Synchronous/Asynchronous Receiver/Transmitter 3 36 (UART0): Universal Asynchronous Receiver/Transmitter 0 37 (TIMER0): Timer 0 38 (TIMER1): Timer 1 39 (WTIMER0): Wide Timer 0 40 (WTIMER1): Wide Timer 1 41 (CM0P): undefined |
| EDSEL | Edge Detect Select 0 (OFF): Signal is left as it is 1 (POSEDGE): A one HFCLK cycle pulse is generated for every positive edge of the incoming signal 2 (NEGEDGE): A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal 3 (BOTHEDGES): A one HFCLK clock cycle pulse is generated for every edge of the incoming signal |
| STRETCH | Stretch Channel Output |
| INV | Invert Channel |
| ORPREV | Or Previous |
| ANDNEXT | And Next |
| ASYNC | Asynchronous Reflex |